1. Field of the Invention
The present invention relates to a differential comparator, an analog/digital conversion apparatus and an imaging apparatus, more particularly, to a technology effective when applied to the reading circuit of optical/electrical conversion signals in a complementary metal oxide semiconductor (CMOS) image sensor and the like.
2. Description of the Related Art
Attention is paid to a CMOS image sensor, for example, for the reason that the CMOS image sensor matches the manufacturing process, operating voltage and the like in surrounding image processing circuits, and that an imaging apparatus, an image processing circuit, a controller and the like can be easily integrated on one chip and the like, compared with, for example, a charge-coupled device (CCD) image sensor.
Since this CMOS image sensor amplifies not only a photoelectric conversion device but also a conversion signal at each pixel level, the CMOS image sensor is resistant to noise in the transmission process of a photoelectric conversion signal. However, its fixed pattern noise due to the unevenness in a characteristic among amplifiers at each pixel level is a problem.
For this reason, a configuration in which the same number of correlation double sampling (CDS) circuits and analog/digital conversion (ADC) circuits as the number of columns are disposed in series for each set of pixels in the column direction, of a plurality of pixels two-dimensionally arrayed in the orthogonal row and column directions, that is, a configuration in which the fixed pattern noise is reduced by a so-called column ADC method, is well known.
As the column ADC of the CMOS image sensor, for example, Patent Reference 1 discloses a technology for realizing fine color control for each color by selectively outputting a different analog comparison reference voltage for a pixel column ADC provided for each color filter of three primary colors of light. Specifically, the accuracy of digital conversion is attempted to improve by short-circuiting the input/output of a chopper type comparator using an inverter and shifting the reference voltage by the same as the shifted value of a threshold voltage, due to the parasitic capacitance of a transistor constituting the relevant inverter.
Patent Reference 2 discloses a technology for eliminating fixed pattern noise that can exist in pixels to improve image quality, by adding a capacitor on the ramp signal input side of a chopper type comparator in which an inverter is connected in double stages, storing offset voltage in the reset mode of a pixel and correcting the voltage of a ramp signal inputted in the counter mode by the offset voltage.
Patent Reference 3 discloses a technology for realizing a stable analog/digital conversion characteristic by shifting the reference voltage of an inverter constituting an AD converter and controlling so that a signal outputted from a pixel and the reference voltage may be compared if the relevant reference voltage has a linear characteristic.
Patent Reference 4 discloses a technology for preventing a direct current level from differing among a plurality of pixel reading signals to improve image quality, by providing a plurality of analog/digital converters, selecting the output of the plurality of analog/digital converters one after another, constituting a noise cancel (comparison) unit of a plurality of amplifiers composed of a differential amplifier and an inverter in a fixed imaging device for obtaining digital picture output and by providing amplifiers at the second stage and after with a clamp circuit.
However, any of the above-mentioned technologies of Patent References 1 through 4 does not recognize the following technical problems caused when the comparator of the analog/digital converter is composed of only an inverter, or an inverter and a differential amplifier.
Specifically, FIG. 1 is a block diagram showing the configuration of a chopper type comparator, which is the reference technology of the present invention. The chopper type comparator using an inverter A100 shown in FIG. 1 stores an analog signal in C100 when switches S100 and S100x are switched on, and compares the analog signal with reference voltage when S100 and S100x are turned off and S200 is turned on to determine the analog signal. However, there is at a point B a parasitic capacitor (C200), such as the gate capacitor of a transistor constituting the inverter A100 or the like. Therefore, if the reference voltage is inputted for comparison, the potential at a point A, point B attempts to transit to the potential of the amount of charge stored in C100 based on the potential at point A. However, since there is the parasitic capacitor C200, point B changes at a ratio between C100 and C200, and the accuracy of analog/digital conversion degrades, which is a technical problem.
Specifically, as shown in FIG. 2, in the inverter A100 of the CMOS imaging sensor, a p type MOS transistor Q100 and a n type MOS transistor Q200 (threshold value Vth) are provided in series between power supply VDD and grounding, and their respective gates and voltage between their sources are used as input and output (OUT), respectively. However, the parasitic capacitor Qp and Qn of Q100 and Q200, respectively, affect capacitor C100 on the input side. Therefore, for example, when SW100 and SW200 are turned off and on, respectively, and when RampV is inputted, the respective gate potential Q100 and Q200 fluctuates at a ratio of Vth-C100 (ADC-RampV)/(C100+Cp+Cn) and the accuracy of analog/digital conversion degrades.
In a configuration using an inverter, the consumption current of the inverter is high. More particularly, in a configuration where a lot of ADC is provided for each column, like column ADC in the CMOS image sensor, the total consumption current of the imaging device becomes very high. As the countermeasure, it may be considered to increase the respective gate length of Q100 and Q200 to suppress the consumption current. However, this is not preferable, since the respective parasitic capacitance Qp and Qn becomes far larger due to the increase of each gate area.    Patent Reference 1: Japanese Patent Application Laid-open No. 2000-261602    Patent Reference 2: Japanese Patent Application Laid-open No. 2002-218324    Patent Reference 3: Japanese Patent Application Laid-open No. 2000-286706    Patent Reference 4: Japanese Patent Application Laid-open No. 2000-287137